ExCALIBUR at SuperComputing 2023

SuperComputing (SC) is the HPC community’s largest conference and, with approximately 15,000 attendees, is always a very busy week with many different activities going on. There will be numerous ExCALIBUR based activities happening at SC this year, with a range of projects represented and involvement in the conference.

The first ExCALIBUR activity of the conference will be where the xDSL project presents their paper entitled “Fortran Performance Optimisation and Auto-Parallelization by Leveraging MLIR-Based Domain Specific Abstractions in Flang” at the LLVM-HPC workshop on the Sunday morning. Fortran is the lingua franca of HPC code development, and this paper describes work done enhancing Flang by bringing in domain-specific abstractions, and a preprint is available here. This paper presentation will be followed by the xDSL project being involved in a panel at the end of the workshop, where the themes and topics identified during the session will be explored and discussed.

On the afternoon of Monday, 13^th November, the Second International Workshop on RISC-V for HPC is running whose organisation has been led by the RISC-V H&ES testbed. This half day workshop will explore the challenges and opportunities of adopting RISC-V in HPC and there is a packed programme of events. The workshop will begin with an invited talk given by Mark Himelstein, the CTO of RISC-V International, and will then follow with four vendor lightening talks to highlight the current product pipeline for RISC-V in HPC. This will then be followed by six research papers presented which represent the state of the art in this topic.

One paper being presented at the RISC-V for HPC workshop on the Monday afternoon is entitled “Is RISC-V Ready for HPC Prime-Time: Evaluating the 64-Core Sophon SG2042 RISC-V CPU” and reports work done by the H&ES RISC-V testbed project. This explores benchmarking of the world’s first commodity 64-core high performance RISC-V CPU using the RAJAPerf benchmarking suite, comparing against other RISC-V commodity CPUs and x86 CPUs currently used for HPC workloads. A preprint of this paper is available here

The Monday evening at SC is the exhibition grand opening gala party, with ExCALIBUR project partners STFC (1953), EPCC (313), and UCL (2143) having booths. There will be information about ExCALIBUR available on each of these stands, as well as some freebees for people to take home, and people who can provide more information about the programme and the activities that we are doing.

On Tuesday, 14^th November, the Birds of a Feather (BoF) “HPC Next: The RISC-V Ecosystem” will be running between 5:15pm and 6:45pm. This will be an opportunity to explore and discuss with the HPC community, the benefits that RISC-V can bring to HPC and how we can best further develop the software ecosystem. The RISC-V H&ES testbed are involved in this BoF, talking at the session and then part of the discussion panel, from the perspective of sharing experiences from an HPC testbed that uses this technology and lessons learnt.

On the Wednesday lunchtime, 12:15pm to 1:15pm, the BoF “Interactive and Urgent HPC” is happening, and this is part organised by the xDSL project. In this session we will be discussing enhancements to the HPC ecosystem to support the use of interactive and urgent computing, with the xDSL project working in this area through Domain Specific Languages (DSLs). This is followed on the Thursday, 16^th November, where ExCALIBUR will be talking at the “Advanced Architecture “Playgrounds” – Past Lessons and Future Accesses of Testbeds” BoF which runs from 12:15pm to 1:15pm, where we will be giving a talk describing the novel testbeds funded by the H&ES programme and lessons learnt from these activities.

Whilst SC finishes Friday lunchtime, the Friday morning, 17^th of November, will be busy for the ExCALIBUR programme because there are numerous workshop activities that will be going on. The CompBioMedX project are organising the “Digital Twins: Practices and Principles for High Performance Computing” workshop which will explore the combination of sensor data with surrogate models in order to enable HPC-based digital twins which are already delivering breakthroughs in computational biomedicine, nuclear fusion, and building automation. The workshop programme involves a variety of talks which explore this subject in detail followed by a panel discussion.

The H&ES benchmarking project are presenting a paper entitled “Principles for Automated and Reproducible Benchmarking” in the HPCTESTS workshop, also on the Friday morning. Describing the methodology adopted by this ExCALIBUR project for measuring and analyzing the performance portability of parallel applications, this paper presentation is aiming to share the ExCALIBUR benchmarking software framework with the wider SC community that can be easily extended to new HPC technologies and use-cases. The benchmarking project are also involved in a panel discussion at the same workshop, which will discuss the themes identified during the session.

Also on the Friday morning, the paper “Stencil-HMLS: A Multi-Layered Approach to the Automatic Optimization of Stencil Codes on FPGA” will be presented at the H2RC workshop. This paper reports work undertaken by a PhD student at EPCC in collaboration with the xDSL project, leveraging and enhancing the xDSL ecosystem to enable auto-optimisation of stencil-based codes for FPGAs, typically delivering orders of magnitude increase in performance for the weather and climate benchamarks that have been explored. The preprint is available here

It therefore promises to be a busy week at SC, if you are at the conference and want to find out more about the ExCALIBUR programme then please drop by the STFC (1953), EPCC (313), or UCL (2143) booths and we would be very happy to chat to you further.