RISC-V

RISC-V is an open-source Instruction Set Architecture (ISA) that continues to grow rapidly since it was introduced over a decade ago. Overseen by RISC-V International, open standards are produced that the community, ranging from companies, academics, and hobbyists, are then free to implement via their own specific microarchitecture. A rich ecosystem has built up around RISC-V, with a great many implementations (many themselves open source) available. There is a growing interest in the use of RISC-V for HPC, including an official RISC-V HPC special interest group and events at leading HPC conferences.

This project is focussed on providing a RISC-V testbed system and supporting the development of enabling software to enable researchers predominantly within ExCALIBUR, but also the wider HPC community, to port their scientific and data-science applications to RISC-V CPUs and explore the performance properties such processors provide. This testbed forms an important UK resource, and one that is unique, for enabling the convenient exploring the role of this technology by application developers and researchers. We provide a mixture of physical and soft-core RISC-V CPUs, the former enabling user exploration with more mature RISC-V solutions, and the later enabling users to experiment with less mature next generation technology which we are also able to tune for select use-cases.

The project has provided the testbed itself, and Research Software Engineer (RSE) effort is being used to develop the soft-core multi-core RISC-V CPU configurations and enabled us to optimise specific HPC and data-science libraries for the architecture as well we develop tools that can aid adoption of RISC-V by the community. Access to the testbed is free and we very much welcome users to sign up and start using this exciting technology. You will find a familiar set of compilers and HPC libraries available via the module environment, and exciting hardware to experiment with. See the website for more details.