First International workshop on RISC-V for HPC

Co-located with ISC 2023, this half day workshop is being led by the RISC-V H&ES ExCALIBUR testbed project and  aims to bring together those already looking to popularise RISC-V in the field of HPC with the supercomputing community at-large. RISC-V is an open standard Instruction Set Architecture (ISA) which enables the royalty free development of CPUs and a common software ecosystem to be shared across them. Following this community driven ISA standard, a very diverse set of CPUs have been, and continue to be, developed which are suited to a range of workloads. Whilst RISC-V has become very popular already in some fields, and in 2022 the ten billionth RISC-V core was shipped, to date it has yet to gain traction in HPC.

Furthermore, recent advances in RISC-V make it a more realistic proposition for HPC workloads than ever before and this is an opportunity not only for HPC developers to gain familiarity and awareness of this new architecture, but furthermore for the HPC community to help drive the evolution of RISC-V to ensure that it is fully suited to our needs.

There is a call for papers open until 24^th March, with more details on our website at https://riscv.epcc.ed.ac.uk/community/isc23-workshop/