The RISC-V Summit Europe brings together all those, predominantly in Europe but also in the wider world, who are working on RISC-V across a wide range of fields. Comprising three days of talks with further members only and workshop days, this is a busy week long event with an opportunity to connect with many companies and individuals working in the field. It has been estimated that there are over 13 billion RISC-V devices, and Europe is a power house of RISC-V development and research including activities such as the European Processor Initiative (EPI).
Nick Brown from the ExCALIBUR H&ES RISC-V testbed recently took over as chair of the HPC SIG this year and-so led a special session during the members day on the HPC SIG. Updating members about latest progress, and getting their feedback on the current areas of focus including a gap analysis to explore the current ecosystem strengthens and weaknesses. This was a busy session, with invaluable feedback from the community and lots of discussions along with people volunteering to help on specific areas which is always nice.
The H&ES RISC-V testbed also presented a poster RISC-V for HPC: Where we are and where we need to go which explored the current state of the art in RISC-V for HPC and detailed where we need to go as a community to help drive adoption of RISC-V for HPC.
RISC-V is growing phenomenally quickly, and it’s always fascinating to attend these events because it demonstrates very clearly the changes from one year to the next. Compared to when we began the testbed in 2022, there are a very large number of new technologies and hardware available – with the ExCALIBUR H&ES RISC-V testbed being one of the world leaders in making this available. Therefore I am excited to see how things continue to progress and new products that will likely be released later this year that could be very interesting for HPC.