ExCALIBUR events @ ISC ‘23

Starting on Sunday the 21st of May and running until Thursday 25th, the HPC and ML community will descend on Hamburg for ISC, which is Europe’s largest HPC conference. Running since 1986, and with 158 exhibitors this year, ISC is always a busy event with many different things going on throughout the week. The ExCALIBUR programme is strongly represented at ISC, with individual projects organising and participating in many activities. So please drop in, say hello, and discuss with us more what is going on in the programme.


The first ExCALIBUR event is a Birds of a Feather (BoF) session on Monday, running 1pm to 2pm in Hall F entitled “Supercomputing and Scientific Code Coupling”. This is being organised by the ExCALIBUR Coupling, Synthesis, and Performance project and will explore the state of the art in scientific code coupling. Building on a very successful BoF at SC22, this session aims to further connect the coupling community and share highlights from global activities underway.

This is then followed by the project poster session opening at 3pm, where both the xDSL and RISC-V H&ES testbed projects will have project posters up all week. If you drop by at 3pm you will be able to chat with project representatives to learn more about these activities.

Between 4:50pm and 5:15pm the research paper “Efficient GPU Offloading with OpenMP for a Hyperbolic Finite Volume Solver on Dynamically Adaptive Meshes” will be presented in Hall 4. This reports work done in the MGHyPE, task-based parallelism and PAX-HPC ExCALIBUR projects to enable effective exploitation of GPUs via OpenMP for this important workload.

Monday evening is party time, with the exhibition opening reception starting at 6:30pm. Both EPCC and STFC have booths at ISC, so please feel free to drop by booth G715 (EPCC) and G712 (STFC) to learn more about ExCALIBUR and what the programme is up to.


Tuesday morning sees the xDSL project represented at the “Plasma-PEPSC – Pushing Flagship Plasma Simulation Codes to Tackle Exascale-Enabled Grand Challenges via Performance Optimisation and Codesign” BoF, which is running 9am to 10am in Hall E. xDSL are contributing their perspectives around the role that domain specific languages can play in this grand challenge scale topic.


The RISC-V H&ES testbed is a co-organiser of, and speaking at, the “RISC-V is HPC. Help Build Your Ecosystem” BoF, which is running between 9am and 10am in Hall 4. This session will explore the benefits that RISC-V can bring to HPC, as well as some of the current challenges and a community call to action. The ExCALIBUR project will be contributing experiences gained by running an HPC style RISC-V testbed as well as advertising how users can gain access to this resource.


Thursday is workshop day at ISC, which is always a busy and varied day with lots going on. The xDSL project is involved in organising the “Second Combined Workshop on Interactive and Urgent Supercomputing” workshop which is running between 9am and 1pm in Hall Y6 and will be exploring challenges that our community faces in enabling interactive and urgent workloads on supercomputers.

The task-based parallelism and Storage and RAM As A Service projects are presenting a paper entitled “Intelligent algorithms on intelligent networks—experiences and challenges using NVIDIA’s BlueField technology” at the “International Workshop on Smart Networks, Data Processing and Infrastructure Units” workshop between 10:30am and 11:00am in Hall Y11. This will highlight how research developed in these ExCALIBUR projects have made available the BlueFIeld technology and enabled users to effectively exploit this.

Thursday afternoon is the “First International Workshop on RISC-V for HPC” running between 2pm and 6pm in Hall Y3. This promises to be a busy event for ExCALIBUR because, not only is the RISC-V H&ES testbed project leading the organisation of this workshop in collaboration with the RISC-V HPC SIG, but furthermore has two research papers being presented during the session. The first, “Test-driving RISC-V Vector hardware for HPC” between 3pm and 3:20pm highlights the state of the art in relation to RISC-V vector hardware, which is very important in obtaining performance with HPC and ML codes. The second paper presentation, “Backporting RISC-V vector assembly”, between 4:50pm and 5:10pm, reports work done to enable version 1.0 of RISC-V vector assembly, which is generated by compilers, to leverage the physical hardware which tends to only support version 0.7.

Drop in at any time!

A major component of these conferences is to meet new people and how we can connect our activities, and we are always very keen to chat about what we are doing. As mentioned, both EPCC and STFC have exhibition booths, G715 and G712 respectively, where we will have information material about the programme and individual projects.