FPGA testbed

This testbed system, and associated effort for enabling software, is aimed at allowing researchers to port their scientific and data-science applications to Field Programmable Gate Arrays (FPGAs) and explore performance and power advantages such technology provides. Composed of next-generation hardware and software, this will form an important UK resource for exploring the future role of FPGA technology in science, engineering, and the broader computational science communities.

In addition to the testbed hardware itself the project is supported by Research Software Engineer (RSE) effort to develop the software stack to enable easier usage of FPGAs, which will be driven by specific use cases from the Excalibur Design and Development Working Groups and other interested application communities.

Project partners EPCC, UCL, and Warwick will work in collaboration with FPGA vendor Xilinx, Inc. the leader in adaptive and intelligent computing, to deliver and operate the testbed.

It is their intention that this will be a first step towards building a future community and ecosystem around the role of FPGAs in HPC, data science, AI, and machine learning workloads in the UK. The project will also be running a series of training events and workshops, and developing training material to ensure the system is accessible and usable.

The testbed will be physically based in EPCC’s Advanced Compute Facility, and will be made publicly available. It will form a unique resource within UK academic computing, as a single system that provides access to next-generation Versal Adaptive Compute Acceleration Platform (ACAP) technology from Xilinx, which includes their revolutionary AI engines; hierarchical memory hardware provision, with high bandwidth (HBM2) and Non-Volatile (NVRAM) memory on some of the hosted hardware, providing a unique resource for software developers and algorithm designers to investigate this emerging field in computing hardware; multiple networking options including a high performance node-level network and direct FPGA to FPGA networking to enable system designers and applications developers to assess the relative merits of both approaches; and multiple families of FPGA, allowing evaluation of a range of technologies by users.

The system will be hosted within an existing, established and modern HPC system which provides sufficient resources to enable developers to quickly and efficiently develop application kernels, synthesise their FPGA bitstreams and test their codes in emulation. Finally, the RSE effort will provide an enabling software stack that should significantly reduce the barrier to entry in utilising FPGAs for scientific and data-science applications.

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