FPGA testbed

Access arrangementshttps://fpga.epcc.ed.ac.uk/
OrganisationsEPCC, University of Edinburgh, University College London, University of Warwick
Project linkageExaClaw, ExCALIBUR-HEP, ELEMENT

This testbed system and associated effort for enabling software, allows researchers to port their scientific and data-science applications to Field Programmable Gate Arrays (FPGAs) and explore performance and power advantages such technology provides. Composed of next-generation hardware and software, the testbed forms an important UK resource for exploring the future role of FPGA technology in science, engineering, and the broader computational science communities.

In addition to the testbed hardware itself the project has been supported by Research Software Engineer (RSE) effort to develop the software stack to enable easier usage of FPGAs, driven by specific use cases from the Excalibur Design and Development Working Groups and other interested application communities.

Project partners EPCC, UCL, and Warwick worked in collaboration with FPGA vendor Xilinx, Inc to deliver and operate the testbed. The testbed is envisaged as the foundation of a future community and ecosystem around the role of FPGAs in HPC, data science, AI, and machine learning workloads in the UK. To this end the project has run a series of training events and workshops, and developed training material to ensure the system is accessible and usable.

The testbed provides access to next-generation Versal Adaptive Compute Acceleration Platform (ACAP) technology from Xilinx, including their revolutionary AI engines; hierarchical memory hardware provision, with high bandwidth (HBM2) and Non-Volatile (NVRAM) memory on some of the hosted hardware, providing a unique resource for software developers and algorithm designers to investigate this emerging field in computing hardware; multiple networking options including a high performance node-level network and direct FPGA to FPGA networking to enable system designers and applications developers to assess the relative merits of both approaches; and multiple families of FPGA, allowing evaluation of a range of technologies by users.

Additionally, RSE effort has been dedicated to providing an enabling software stack to significantly reduce the barrier to entry in utilising FPGAs for scientific and data-science applications.

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