ExCALIBUR at Supercomputing 2024

With around 15,000 attendees, Supercomputing (SC) is the HPC community’s largest global conference. It is always a great opportunity to connect with a wide range of members in the community across many disciplines. Programme partners EPCC (booth 1101), STFC (booth 4331) and UCL (booth 4031) being on the exhibition show floor, happy to chat about the programme and with some branded merchandise for grabs!

There will be a variety of ExCALIBUR activities and events happening at SC24. The first day of SC, Sunday 17th, sees the The 2nd Digital Twins Workshop for High-Performance Computing all-day workshop which is organised by the CompBioMedX and CompBioMedEE projects. A computational representation of a real world object, known as a digital twin, provides many opportunities for experimentation that is not possible with the physical item and this has many potential applications ranging from engineering all the way to medicine. The workshop will be not only highlighting the range of application areas, and identifying latest trends and techniques, but in the afternoon will pivot focus towards sustainability and energy efficiency of HPC.

The Monday, 18th, is a busy day with the xDSL project presenting a paper Fully integrating the Flang Fortran compiler with standard MLIR at the Tenth Workshop on the LLVM Compiler Infrastructure in HPC between 12 noon and 12:30pm. The paper explores connecting the open source Fortran Flang compiler with the standard MLIR ecosystem, which then results in several benefits ranging from increased performance to better flexibility.

On the Monday afternoon the RISC-V H&ES testbed is running the International Workshop on RISC-V for HPC, between 2pm and 5:30pm, which has a very exciting line up of speakers including the CEO and Founder of Esperanto technologies, the director of technical programmes at RISC-V International and vendors including Tenstorrent, InspireSemi and E4 Computer Engineering. As this workshop the RISC-V H&ES testbed is also presenting a paper Accelerating stencils on the Tenstorrent Grayskull RISC-V accelerator between 4:50pm and 5:10pm, which is the first exploration of scientific computing workloads on a RISC-V PCIe accelerator and leverages Tenstorrent’s accelerator to speed up stencil computations at significantly reduced power draw.

On the Wednesday afternoon, between 1:30pm – 3pm the RISC-V H&ES testbed is running a panel RISC-V and HPC: How Can We Benefit from the Open Hardware Revolution? The objective of this is to sit down with a wide range of voices from across the RISC-V and HPC communities, and explore how we can continue to bring these two areas together to ensure that RISC-V is able to address some of the grand challenges faced by HPC for example around energy efficiency.

Later on the Wednesday, between 5:15pm – 6:45pm, the Democratizing AI Accelerators for HPC Applications: Challenges, Success, and Support Birds of a Feather (BoF) collaborative session will explore leveraging the wide range of AI accelerators for scientific computing. As many of these accelerators are built to speed up computation, there is an opportunity to also use them for a much wider range of applications than they were initially intended, and indeed the Hardware and Enabling Software (H&ES) Cerebras testbed and FPGA testbed have been doing exactly this and are involved in organising and speaking at this session.

On the Thursday the xDSL project is organising the MLIR for HPC: An Opportunity to Revolutionize HPC Programming Tools BoF session between 12:15pm and 1:15pm, with one member of the project chairing the session and another involved as a speaker. The idea is to bring experts in the MLIR technology together in the room, along with those interested more generally in compilers and optimisation for HPC codes, to discuss how the community can best leverage MLIR and what needs to be done to ensure that it works for us.

On the Friday the xDSL project is involved in organising the Fourth Combined Workshop on Interactive and Urgent HPC which is running between 8:30am and 12 noon, with a focus on interactive workloads on HPC machines. Furthermore, in the Tenth International Workshop on Heterogeneous High-performance Reconfigurable Computing the xDSL and FPGA H&ES testbed are giving an invited talk Lowering the Barriers to Programming FPGAs and AIEs for HPC between 9:20am and 9:40am, describing the collaboration between these ExCALIBUR projects which has significantly reduced the barrier to entry in programming the FPGA and AI Engine hardware technologies for HPC codes.

ExCALIBUR @ SC24 at a glance

When	What	Where
Sunday, 17th, 9am to 5:30pm	Workshop:The 2nd Digital Twins Workshop for High-Performance Computing	B308
Monday 18th, 12 noon to 12:30pm	Paper: Fully integrating the Flang Fortran compiler with standard MLIR	B310
Monday 18th, 2pm to 5:30pm	Workshop: International Workshop on RISC-V for HPC	B315
Monday 18th, 4:50pm to 5:10pm	Paper: Accelerating stencils on the Tenstorrent Grayskull RISC-V accelerator	B315
Wednesday 20th, 1:30pm to 3pm	Panel: RISC-V and HPC: How Can We Benefit from the Open Hardware Revolution?	B313B-B314
Wednesday 20th, 5:15pm to 6:45pm	BoF: Democratizing AI Accelerators for HPC Applications: Challenges, Success, and Support	B211
Thursday 21st, 12:15pm to 1:15pm	BoF: MLIR for HPC: An Opportunity to Revolutionize HPC Programming Tools	B308
Friday 22nd, 8:30am to 12 noon	Workshop: Fourth Combined Workshop on Interactive and Urgent HPC	B315
Friday 22nd, 9:20am to 9:40am	Invited talk: Lowering the Barriers to Programming FPGAs and AIEs for HPC	B208